CadenceCONNECT:
Technology Forum 2025
Greater Noida
Summary
Join us at the Cadence Technology Forum in Greater Noida on April 1, 2025. Discover how Cadence solutions can address your toughest custom, digital, and verification design challenges while improving speed and profitability.
This full-day event will feature:
- Expert insights – Discover the latest Cadence products, flows, and methodologies to enhance the development of silicon, SoCs, and systems, enabling you to create advanced technologies faster and more profitably.
- Best practices shared by your peers on how they are using Cadence technologies effectively.
- Interactive discussions with Cadence R&D team members on technology, roadmaps, and use cases.
The event will feature three tracks covering Custom and Analog Design, Digital Design, and System Design and Verification.
Event Details:
Date: April 1, 2025
Time: 10:00AM - 4:30PM
Location: Hotel Crowne Plaza Greater Noida, Surajpur Chowk, Greater Noida
Agenda:
| Custom and Analog Design Track | |
| Timing | Topic |
| 9:00 - 10:00 | Registration |
| 10:00 - 11:00 | Accelerating Custom Designs using Virtuoso Studio and Quantus Insight |
| 11:00 - 11:30 | MMSIM 25.1 Technology Update |
| 11:30 - 11:45 | Tea Break |
| 11:45 - 12:15 | Liberate/MX Trio Characterization Suite |
| 12:15 - 13:00 | Panel Discussion: AI in Analog Designs - Challenges and Solutions |
| 13:00 - 13:45 | Lunch Break |
| 13:45 - 14:15 | ST Presentation: Custom Digital APR for Analog on Top Design using Virtuoso-MXL |
| 14:15 - 14:45 | NXP Presentation: Accelerating Precise and Efficient Design Porting Across Foundries |
| 14:45 - 15:15 | ST Presentation: Bus and Advanced Interactive Routing Using Virtuoso Studio |
| 15:15 - 15:45 | NXP Presentation: Spectre-FX in Full-Chip Spice Simulation |
| 15:45 - 16:15 | ST Presentation: Fast Monte Carlo Analysis in Automotive IP |
| 16:15 - 16:30 | Closing Ceremony and Best Presentation Award |
| Digital Design and Signoff Track | |
| 9:00 - 10:00 | Registration |
| 10:00 - 11:00 | Advanced Techniques for Full-Flow PPA Optimization |
| 11:00 - 11:15 | Tempus Timing Signoff Solution Technology Update |
| 11:15 - 11:30 | Tea Break |
| 11:30 - 12:15 | Optimization and Closure for Block-Level and Subsystem-Level With Tempus ECO and Cadence Certus Closure Solution |
| 12:15 - 13:00 | Accelerate IR Signoff with Voltus InsightAI and Voltus XM |
| 13:00 - 13:45 | Lunch Break |
| 13:45 - 14:15 | Next Generation Cerebrus: AI Driven Multi Block / SoC Design Platform |
| 14:15 - 14:45 | ST Presentation: Effort and Cycle Time Reduction in Design Closure Using Cadence AI Tools |
| 14:45 - 15:15 | NXP Presentation: Dynamic Methodology to Accelerate Power Structure Implementation using FLASH PG |
| 15:15 - 15:45 | ST Presentation: Maximizing Power Efficiency and Performance of Cortex M85 Subsystems with Cadence Solutions |
| 15:45 - 16:15 | NXP Presentation: Efficient Rush Current Analysis for Power Gated Design |
| 16:15 - 16:30 | Closing Ceremony and Best Presentation Award |
| System Design and Verification Track | |
| 9:00 - 10:00 | Registration |
| 10:00 - 10:40 | Advancements in Verification |
| 10:40 - 11:10 | Jasper Technology Update and Roadmap |
| 11:10 - 11:40 | NXP Presentation: The Silent Sentinel - Verifying Neural Networks from Design to Deployment |
| 11:40 - 12:00 | Tea Break |
| 12:00 - 12:30 | Qualcomm Presentation: Liveness Assume-Guarantee Proof Schema: A Step Towards Liveness Full Proofs |
| 12:30 - 13:00 | NXP Presentation: Regression Run Time Optimization Using Verisium Smart Run |
| 13:00 - 13:45 | Lunch Break |
| 13:45 - 14:15 | Hardware Technology Update |
| 14:15 - 14:45 | System Solution Overview |
| 14:45 - 15:15 | NXP Presentation: Comprehensive Exploration of Low Power Modes and Wake-Up Scenarios with Perspec |
| 15:15 - 15:45 | ST Presentation: Innovation Verification Strategies for Enhancing Efficiency, Coverage and Bug Hunting |
| 15:45 - 16:15 | NXP Presentation: Optimizing Simulation Runtime Efficiency: Techniques for Enhanced Performance |
| 16:15 - 16:30 | Closing Ceremony and Best Presentation Award |
